Controlled collapse chip connection (C4) or flip-chip technology has been successfully used for over twenty years for interconnecting high I/O (input/output) count and area array solder bumps on the silicon chips to the base ceramic chip carriers, for example alumina carriers. The solder bump, typically a 95 Pb/5 Sn alloy, provides the means of chip attachment to the ceramic chip carrier for subsequent usage and testing. For example, see U.S. Pat. Nos. 3,401,126 and 3,429,040 to Miller and assigned to the assignee of the present application, for a further discussion of the controlled collapse chip connection (C4) technique of face down bonding of semiconductor chips to a carrier. Typically, a malleable pad of metallic solder is formed on the semiconductor device contact site and solder joinable sites are formed on the chip carrier.
The device carrier solder joinable sites are surrounded by non-solderable barriers so that when the solder on the semiconductor device contact sites melts, surface tension of the molten solder prevents collapse of the joints and thus holds the semiconductor device suspended above the carrier. With the development of the integrated circuit semiconductor device technology, the size of individual active and passive elements have become very small, and the number of elements in the device has increased dramatically. This results in significantly larger device sizes with larger number of I/O terminals. This trend will continue and will place increasingly higher demands on device forming technology. An advantage of solder joining a device to a substrate is that the I/O terminals can be distributed over substantially the entire top surface of the semiconductor device. This allows an efficient use of the entire surface, which is more commonly known as area bonding.
Usually the integrated circuit semiconductor devices are mounted on supporting substrates made of materials with coefficients of expansion that differ from the coefficient of expansion of the material of the semiconductor device, i.e. silicon. Normally the device is formed of monocrystalline silicon with a coefficient of expansion of 2.6.times.10.sup.-6 per .degree.C. and the substrate is formed of a ceramic material, typically alumina with a coefficient of expansion of 6.8.times.10.sup.-6 per .degree.C. In operation, the active and passive elements of the integrated semiconductor device inevitably generate heat resulting in temperature fluctuations in both the devices and the supporting substrate since the heat is conducted through the solder bonds. The devices and the substrate thus expand and contract in different amount with temperature fluctuations, due to the different coefficients of expansion. This imposes stresses on the relatively rigid solder terminals.
The stress on the solder bonds during operation is directly proportional to (1) the magnitude of the temperature fluctuations, (2) the distance of an individual bond from the neutral or central point (DNP), and (3) the difference in the coefficients of expansion of the material of the semiconductor device and the substrate, and inversely proportional to the height of the solder bond, that is the spacing between the device and the support substrate. The seriousness of the situation is further compounded by the fact that as the solder terminals become smaller in diameter in order to accommodate the need for greater density, the overall height decreases.
The disclosure of an improved solder interconnection structure with increased fatigue life can be found in U.S. Pat. No. 4,604,644 to Beckham, et al. and assigned to the assignee of the present application, disclosure of which is incorporated herein by reference. In particular, U.S. Pat. No. 4,604,644 discloses a structure for electrically joining a semiconductor device to a support substrate that has a plurality of solder connections where each solder connection is joined to a solder wettable pad on the device and a corresponding solder wettable pad on the support substrate, dielectric organic material disposed between the peripheral area of the device and the facing area of the substrate, which material surrounds at least one outer row and column of solder connections but leaves the solder connections in the central area of the device free of dielectric organic material.
The preferred material disclosed in U.S. Pat. No. 4,604,644 is obtained from a polyimide resin available commercially and sold under the trademark AI-10 by Amoco Corporation. AI-10 is formed by reacting a diamine such as p,p' diaminodiphenylmethane with a trimellitic anhydride or acylchloride of trimellitic anhydride. The polymer is further reacted with .gamma.-amino propyl triethoxy silane (A-1100) or .beta.-(3,4-epoxy cyclohexyl) ethyltrimethoxy silane (A-186) from Dow Corning. The coating material is described in IBM Technical Disclosure Bulletin, September 1970, p. 825.
The dielectric material is typically applied by first mixing it with a suitable solvent and then dispensing it along the periphery of the device where it can be drawn in between the device and substrate by capillary action.
Encapsulants that exhibit, among other things, improved fatigue life of C4 solder connections are disclosed in U.S. Pat. No. 4,999,699 to Christie et al. and assigned to the assignee of the present invention, disclosure of which is incorporated herein by reference. In particular, U.S. Pat. No. 4,999,699 discloses a curable composition containing a binder which is a cycloaliphatic polyepoxide and/or a cyanate ester or prepolymer thereof and a filler. The cycloaliphatic polyepoxide, cyanate ester and cyanate ester prepolymer employed have viscosities at normal room temperatures (25.degree. C.) of no greater than about 1,000 centipoise. The filler has a maximum particle size of 31 microns and is substantially free of alpha particle emissions. The amount of binder (i.e. --epoxy and/or cyanate ester) is about 60 to about 25 percent by weight of the total of the binder and filler and, correspondingly, the filler is about 40 to about 75 percent by weight of the total of the binder and filler.
In addition, U.S. Pat. No. 5,121,190 to Hsiao et al. and assigned to the assignee of the present application, disclosure of which is incorporated herein by reference, discloses providing C4 solder connections of an integrated semiconductor device on an organic substrate. The compositions disclosed therein are curable compositions containing a thermosetting binder and filler. The binder employed has viscosity at normal room temperatures (25.degree. C.) of no greater than about 1,000 centipoise. Suitable binders disclosed therein include polyepoxides, cyanate esters and prepolymers thereof.
The technique disclosed therein enables chips to be attached directly on the surface of a board thereby eliminating an intermediate chip carrier.
Although the above techniques discussed in U.S. Pat. Nos. 4,999,699 and 5,121,190 have been quite successful, there still remains room for improvement, especially with respect to relatively low temperature processability.